summit microelectronics, inc. ? 300 orchard city drive, suite 131 campbell, ca 95008 telephone 408-378- 6461 fax 408-378-6586 www.summitmicro.com 1 ? summit microelectronics, inc. 2000 2023 2.2 8/2/00 characteristics subject to change without notice summit microelectronics, inc. features ? four 8-bit dacs ? differential non-linearity: 0.5lsb max ? integral non-linearity error: 1lsb max each dac has independent reference inputs ? output buffer amplifiers swing rail-to-rail ? ground to v dd reference input range each dac?s digital inputs maintained in eeprom power-on reset reloads registers with non- volatile data simple serial interface for reading and writing dac values, spi? and qspi? compatible. fully operational from 2.7v to 5.5v low power, 4mw max at +5v quad 8-bit nonvolatile dacpot? electronic potentiometer with a mute control input s9418 overview the s9418 dacpot? is a serial input, voltage output, quad 8-bit digital to analog converter (dac). the s9418 operates from a single 2.7v to 5.5v supply. internal precision buffers swing rail-to-rail and the reference input range includes both ground and the positive supply. the s9418 integrates four 8-bit dacs and their associ- ated circuits which include; an enhanced unity gain opera- tional amplifier output, an 8-bit data latch, an 8-bit non- volatile register and an industry standard serial interface for reading and writing data to the dacs? data latches and registers. the dacs are independently programmable and each has its own electrically isolated vreference inputs. block diagram v refh0 v out0 18 2 8-bit e 2 prom 8-bit data register serial data in serial data out 8-bit dac amp v dd 3 rdy/bsy# 4 v refl0 9 11 cs# di 7 6 mute clk 5 v refh1 v out1 17 1 v refl1 12 v refh2 v out2 16 20 v refl2 13 v refh3 v out3 15 19 v refl3 14 dac section 0 dac section 1 dac section 2 dac section 3 do 8 memory control programming memory controller control logic gnd 10
2 s9418 2023 2.2 8/2/00 the analog outputs of the s9418 can be programmed to any one of 256 individual voltage steps. each step value is 1/256 th of the voltage differential between v refh and v refl of the respective dac. once programmed these settings can be retained in nonvolatile memory during all power conditions and will be automatically recalled upon a power-up sequence. each dac can be independently read without affecting the output voltage during the read cycle. in addition each output can be adjusted an unlim- ited number of times without altering the value stored in the nonvolatile memory. device operation analog section the s9418 is an 8-bit, voltage output digital-to-analog converter (dac). the dac consists of a resistor network that converts 8-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage. reference inputs the voltage differential between the v refl and v refh inputs sets the full-scale output voltage for its respective dac. v refl must be equal to or greater than ground (positive voltage). v refh must be greater (more positive) than v refl or equal to v dd . pinout and signal definition pin name function 1, 2 v refh vreference high: 19, 20 v refh - v dd > v refl 3v dd power supply voltage 4 rdy/ ready/busy#: open drain output bsy# indicating status of nonvolatile write operations 5 clk clock input pin: used for serial data communication 6 cs# chip select: when high deselects the device and places it in a low power mode 7 di data input: serial data input pin 8 do data output: serial data output pin 9 mute when active forces v out to v refl 10 gnd power supply ground 11, 12 v refl vreference low 13, 14 15, 16 v out dac output: buffered d to a 17, 18 converter output output buffer amplifiers the voltage outputs are from precision unity-gain follow- ers that can slew up to 1v/s. the outputs can swing from v refl to v refh . with a 0v to 5v output transition the amplifier outputs typically settle to 1lsb in 40s. digital interface the s9418 employs a common 4-wire serial interface. it is comprised of a clock (clk), chip select (cs#), data input (di) and data output (do). data is clocked into the device on the clock?s rising edge and out of the device on the clock?s falling edge. data is shifted in and out msb first. do only becomes active after the device has been se- lected and after a valid read command and address has been received. all data transfers are initiated after cs# goes low and a logic ?1? is clocked into the device. this first data transfer is the start bit and must precede all operations. following the start bit are two command bits used to specify which of four commands to execute. the next two bits are the address bits used to select one of the four dacs. the action of the next eight clock cycles will be dependent upon the command issued. v refh1 v refh0 v dd rdy/bsy# clk cs# di do mute gnd v refh2 v refh3 v out0 v out1 v out2 v out3 v refl3 v refl2 v refl1 v refl0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 2023 t pcon 2.0 20-pin pdip or 20-pin soic
s9418 3 2023 2.2 8/2/00 internally there are four dacs and associated with each are two registers. there is one data register that is used by the dac to hold the digital value it converts. there is also one nonvolatile register that holds the default value that can be recalled into the data register during power- up or by executing the recall command. read read operations are initiated by taking cs# low and clocking in a start bit followed by the read command and the address of the data register to be read. the next eight clocks will output on the do pin the contents of the selected data register. this read will not affect the contents of the register or the output of the dac. refer to figure 1 for an illustration of the sequence of bus conditions for a read operation. write write operations are initiated by taking cs# low and clocking in a start bit followed by the write command and the address of the data register to be written. this action is followed by the host clocking eight bits of data into the register, msb first. the output of the selected dac will change as the last bit is clocked into the device. at this point the clock counter will reset the command register, requiring a full sequence to be initiated in order to write to the dac again. refer to figure 2 for an illustration of the sequence of bus conditions for a write operation. note: this write operation does not affect the contents of the nonvolatile register. therefore, the nonvolatile register can contain the power-on default settings (e.g. volume), and the write dac command can be used to make situational adjustments. figure 1. read sequence table 1. t r a t sc 1 c 0 a 1 a 0 d n a m m o c 10 0aa e l b a n e e t i r w v n 10 1aa n i a t a d ? e t i r w 110aa t u o a t a d ? d a e r 111aa l l a c e r s t a r t ca ca 110 0 clk di do hi z dd 10 3 4 5 6 72 dddddd hi z 2023 t fig01 2.0 rdy/bsy# cs# (pulled up to v dd )
4 s9418 2023 2.2 8/2/00 figure 2. write sequence nonvolatile write a nonvolatile write is a two step operation: it is initiated by taking cs# low and clocking in a start bit followed by the nv write enable command. at this point the host can take cs# back high or continue clocking in data. this data is don ? t care and will be ignored by the s9418. next, the host takes cs# low again and issues a write command and address and then clocks in the eight data bits to be programmed. the host will then bring cs# high and the data will be latched into the data register and a nonvolatile write operation will commence. figure 3. nonvolatile write sequence the status of the nonvolatile write can be monitored on the rdy/bsy# pin. a logic low indicates the write is still in progress and the s9418 will not be accessible to the host; a logic high indicates the write has completed and the s9418 is ready for the next command. refer to figure 3 for an illustration of the sequence of bus conditions for a nonvolatile write operation. e s t a r t cd a cd a 10 3 4 5 6 7 11 2 0 0 dddddd clk di do hi z vout 2023 t fig02 2.0 cs# rdy/bsy# (pulled up to v dd ) a 0 1 d clk di rising edge sets nv write enable latch cc 10 cc 10 d ad a 10 3 4 5 6 7 12 0 dddddd address and data are don ? t care rising edge starts nv write nv write enable latch is reset 2023 t fig03 2.0 cs# rdy/bsy#
s9418 5 2023 2.2 8/2/00 figure 4. recall command sequence recall command the recall command will retrieve data from the selected nonvolatile register and write it into the data register of the associated dac. this operation is initiated by taking cs# low and clocking in a start bit followed by the recall command and the address of the nonvolatile register to be recalled. the eight bits of data are don ? t care, so cs# can be taken high any time after the address bits are clocked in. refer to figure 4 for an illustration of the sequence of bus conditions for a recall operation. power-on recall whenever the s9418 is powered on, the v out values will be returned to the analog equivalent of the data byte stored in the nonvolatile register. mute operation the mute input is active high. whenever the input is low the v out will reflect the value in the data register. if mute is driven high the v out outputs will be switched to v refl . releasing the mute input returns the v out outputs to the analog equivalent of the data register contents. s t a r t ca ca 110 0 clk di v out 2023 t fig04 2.0 cs#
6 s9418 2023 2.2 8/2/00 absolute maximum ratings v dd to gnd .................................................................... -0.5v to +7v digital inputs to gnd ............................................. -0.5v to v dd +0.5v analog inputs to ground ....................................... -0.5v to v dd +0.5v digital outputs to gnd .......................................... -0.5v to v dd +0.5v analog outputs to gnd ......................................... -0.5v to v dd +0.5v temperature under bias ........................................... -55 c to +125 c storage temperature ................................................ -65 c to +150 c lead soldering (10 sec max) .................................................... 300 c stresses listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. dc electrical characteristics (over recommended operating conditions unless otherwise specified) condition min max temperature -40 c +85 c v dd +2.7v +5.5v recommended operating conditions 2023 pgm t2 1.1 reliability characteristics (over recommended operating conditions unless otherwise specified) l o b m y sr e t e m a r a pn i mx a mt i n u v p a z y t i l i b i t p e c s u s d s e0 0 0 2v i h t l p u - h c t a l0 0 1a m t r d n o i t n e t e r a t a d0 0 1s r a e y n d n e e c n a r u d n e0 0 0 , 0 0 0 , 1s e l c y c e g a r o t s l o b m y sr e t e m a r a ps n o i t i d n o cn i mp y tx a mt i n u i d d e r o t s g n i r u d t n e r r u c y l p p u s ) 1 e t o n ( v = s c l i 8 . 15 . 2a m i b s t n e r r u c y l p p u s y b d n a t sv = s c h i 0 6 20 0 5a i h i t n e r r u c e g a k a e l t u p n iv n i v = d d 1 <0 1a i l i t n e r r u c e g a k a e l t u p n iv n i v 0 =1 <0 1 ? a v h i e g a t l o v t u p n i l e v e l h g i h v 5 . 4 c c v v 5 . 52 v d d v c c v v 5 . 49 . 0 v c c v d d v v l i e g a t l o v t u p n i l e v e l w o l v 5 . 4 c c v v 5 . 50 8 . 0v c c v v 5 . 401 . 0 v c c v v h o e g a t l o v t u p t u o l e v e l h g i ha 0 0 4 ? = h o iv d d 3 . 0 ? v v l o e g a t l o v t u p t u o l e v e l w o l , a m 1 = l o iv d d ; v 5 = , a m 4 . 0 = l o iv d d v 7 . 2 = 4 . 0v note 1: i dd is the supply current drawn while the eeprom is being updated. typical t a = 25 o c and v cc = 5.0v. 3.0
s9418 7 2023 2.2 8/2/00 figure 5. ac timing diagram symbol parameter conditions min. typ. max. units f c clock frequency dc 1 mhz t wh minimum clk high time 500 ns t wl minimum clk low time 300 ns t cs minimum cs high time 150 ns t css cs setup time 100 ns t csh cs hold time 0 ns t su data in setup time c l = 100pf 50 ns t h data in hold time see note 1 50 ns t v output valid time 150 ns t ho data out hold time 0 ns t dis output disable time 400 ns t busy write cycle time 3.3 5 ms notes: 1. all timing measurements are defined at the point of signal crossing v dd /2. ac electrical characteristics v dd = +4.5v to +5.5v, v refh = v dd , v refl = 0v, t a = -40 c to +85 c, unless otherwise specified 2023 pgm t5 1.1 t ho t dis t cs t wh hi z hi z t su t h t css t wl t v clk di do t csh 2023 t fig05 2.0 rdy/bsy# cs#
8 s9418 2023 2.2 8/2/00 dac electrical characteristics v dd = 2.7v to 5.5v, v refh = vdd, v refl = 0v, t a = ? 40 o c to 85 o c, unless otherwise specified y t r e p o r pl o b m y sr e t e m a r a ps n o i t i d n o cn i mp y tx a mt i n u y c a r u c c a l n iy t i r a e n i l - n o n l a r g e t n ii d a o l a 0 0 1 =5 . 01 b s l l n dy t i r a e n i l - n o n l a i t n e r e f f i di d a o l ) 1 e t o n ( a 0 0 1 =1 . 05 . 0 b s l s e c n e r e f e r v h f e r e g a t l o v t u p n iv l f e r v v l f e r e g a t l o v t u p n id n gv r n i v h f e r v o t l f e r e c n a t s i s e rk 0 4 ? r c t n i r f o t n e i c i f f e o c . p m e t n i 0 0 30 0 6c o / m p p ? r n i h c t a m e c n a t s i s e r t u p n i5 . 0 1 % g o l a n a t u p t u o g s f e r o r r e n i a g e l a c s - l l u ff f = d x e h 1 b s l v t u o s ze g a t l o v t e s f f o t u p t u o0 0 = d x e h 05 . 25 v m v c t t u o v t u o t n e i c e i f f e o c . p m e t v d d i , v 5 = d a o l a 0 5 = ) 1 e t o n ( 0 5c o / v i l t n e r r u c d a o l t u p t u o p m a0 0 2 ? 0 0 0 1a r t u o e c n a t s i s e r t u p t u o p m a v d d v = h f e r v 5 v 3 0 1 0 2 ? ? r r s pn o i t c e j e r y l p p u s r e w o pi d a o l a 0 1 =1v / b s l t s b s l 1 o t e m i t g n i l t t e s c a d f p 0 1v 5 v 3 f p 0 1 6 3 7 2 0 4 5 3 s s e n e s i o n t u p t u o p m av , z h k 1 = f d d v 5 =0 9v n z h d h tn o i t r o t s i d c i n o m r a h l a t o t v h f e r v , v 5 . 2 = d d , v 5 = v , z h k 1 = f n i v 1 = s m r 8 0 . 0% w bb d 3 ? h t d i w d n a b v h f e r v , v 5 . 2 = d d , v 5 = v n i v m 0 0 1 = s m r 0 0 3z h k note 1: guaranteed but not tested. typical t a = 25 o c and v cc = 5.0v.
s9418 9 2023 2.2 8/2/00 20 pin soic (.300) package 0.014 - 0.019 (0.356 - 0.482) 0.004 - 0.012 (0.102 - 0.305) 0.037 - 0.045 (0.940 - 1.143 0.496 - 0.512 (12.598 - 13.005) 0.394 - 0.419 (10.007 - 10.643) 0.093 - 0.104 (2.362 - 2.642) 0.016 - 0.050 (0.406 - 1.270) 0.050 (1.270) 0.009 - 0.013 (0.229 - 0.330) 0.010 - 0.029 (0.254 - 0.737) 0.291 - 0.299 (7.391 - 7.595) 20pn soic ill.1 0 to 8 typ x45 figure 6. v l to v h end-to-end resistance over temperature 41.5 41.0 40.5 40.0 39.5 39.0 resistance (k ? ) temperature ( o c) ? 40 90 25 v l = gnd v h = 5.5v v h = 4.5v v h = 2.7v 2023 t fig06 2.0
10 s9418 2023 2.2 8/2/00 notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2000 summit microelectronics, inc. ordering information package p = 20 pin pdip s = 20 pin soic s9418 p base part number 2023 tree 2.0
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